WDEN=WWDTSTOPPED, WDRESET=WWDTINT, WDPROTECT=NO_LOCK
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
| WDEN | Watchdog enable bit. This bit is Set Only. 0 (WWDTSTOPPED): The watchdog timer is stopped. 1 (WWDTRUN): The watchdog timer is running. |
| WDRESET | Watchdog reset enable bit. This bit is Set Only. 0 (WWDTINT): A watchdog time-out will not cause a chip reset. 1 (WWDTRESET): A watchdog time-out will cause a chip reset. |
| WDTOF | Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit. |
| WDINT | Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit. |
| WDPROTECT | Watchdog update mode. This bit is Set Only. 0 (NO_LOCK): The watchdog time-out value (WDTC) can be changed at any time. 1 (LOCK): The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |